This invention relates generally to program source code compilation, and more particularly to eliminating compares in the prediction phase of compilation.
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In the compilation of program source code, after the compiler performs global optimization, comparison statements in the executable relocatable assembly-computer code are optimized in the prediction phase of compilation to reduce the number of comparison statements generated in the executable code. In conventional predication, fully resolved predicates are implemented to guard or qualify against the execution of an instruction when the data flow equation determines that the particular predicate name is defined on all paths.
Predicate execution code is generated in place of predicted branches. The predicated code is the conditional execution of an instruction under the control of a predicate. By conditionally executing all instructions in a portion of code under guard of a condition, instead of requiring change of control flow, predication effectively eliminates branches from the code. This is beneficial on wide and deep pipelines where the effect of flushes due to branch-miss predictions can cause bubbles in the execution pipeline. This results in a large opportunity cost of instructions that could have been executed. In essence, predication converts a control-dependence branch condition into a data-dependence predicate. Each microprocessor architecture accommodates a fixed number of predicate hardware registers that are used in the predication comparison. The predicate hardware registers represent the predicates that represent conditions that guard against execution of a block of code. The first predicate P0 is hardwired to represent a boolean true.
To optimize comparison statements, a region of a code flow graph is selected within which the optimization is determined, or the optimization analysis is performed. To compute a fully resolved predicate for a selected flow graph region, the control dependence information in the complete flow graph is used.